000 00670nam a2200205Ia 4500
005 20260114154850.0
008 008 250103s9999 xx 000 0 eng d
037 _aTheses
040 _aARTS
_beng
_cARTS
041 _aeng
_2eng
084 _qARTS
100 _aGarg Neha Au.
_9867323
245 0 _aModeling and Simulation of Multigate Junctionless Transistors for low Power VLSI Design
260 _aDelhi
_bUniversity of Delhi. Faculty of Inter- Disciplinary & Applied Science. Deptt. of Electronics Science
_c2022
300 _a124p.
650 _aElectronic Science
_9867324
700 _a Kabra Sneha Gu.
_9867325
942 _cTH
999 _c1468776
_d1468776