00588nam a2200205Ia 450000500170000000800460001703700110006304000080007404000080008204000080009004100080009804100080010608400080011410000510012224500770017326000090025030000100025965000150026970000980028420260430150447.0008  250103s9999    xx            000 0 eng d  aTheses  aCRL  beng  ceng  2eng  aeng  qCRL  aMahendra Mihika Mahesh Au.; Gupta Maneesha Gu. 0aDesign, Analysis and Performances Enhancement of Various Analog Circuits  c2023  a181p.  aTechnology  aUniversity of Delhi. Faculty of Technology. Deptt. of Electronics & Communication Engineering