00758nam a2200241Ia 450000500170000000800460001703700110006304000080007404000080008204000080009004100080009804100080010608400080011410000600012224500770018226000090025930000100026865000150027870001070029394200070040099900210040795200880042820260430150447.0008  250103s9999    xx            000 0 eng d  aTheses  aCRL  beng  ceng  2eng  aeng  qCRL  aMahendra Mihika Mahesh Au.; Gupta Maneesha Gu.91237567 0aDesign, Analysis and Performances Enhancement of Various Analog Circuits  c2023  a181p.  aTechnology  aUniversity of Delhi. Faculty of Technology. Deptt. of Electronics & Communication Engineering91237568  cTH  c1849832d1849832  00104070aCRLbCRLd2026-04-30l0pTH0026923r2026-04-30 15:04:47w2026-04-30yTH