00739nam a2200217Ia 4500003000400000005001700004006001800021007000300039008004100042024001000083037001100093040001800104041001300122100002100135110010400156245010100260260000900361300002300370700002400393700010400417OSt20220930093158.0a|||||r|||| 00| 0ta220926b        |||||||| |||| 00| 0 eng d  a29381  cTheses  aCRLcCRLbeng  2engaeng  aSingh Kunwar Au.  aUniversity of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering 0aDesign and optimization of digital cmos integrated circuits for minimum power-delay-area product  c2015  axxi,218p.ap.ccm.  a Gupta Maneesha Gu.  aUniversity of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering