Modeling and Simulation of Multigate Junctionless Transistors for low Power VLSI Design (Record no. 1468776)

MARC details
000 -LEADER
fixed length control field 00670nam a2200205Ia 4500
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20260114154850.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 008 250103s9999 xx 000 0 eng d
037 ## - SOURCE OF ACQUISITION
Stock number Theses
040 ## - CATALOGING SOURCE
Original cataloging agency ARTS
Language of cataloging eng
Transcribing agency ARTS
041 ## - LANGUAGE CODE
Language code of text/sound track or separate title eng
Source of code eng
084 ## - COLON CLASSIFICATION NUMBER
Assigning agency ARTS
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Garg Neha Au.
9 (RLIN) 867323
245 #0 - TITLE STATEMENT
Title Modeling and Simulation of Multigate Junctionless Transistors for low Power VLSI Design
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Delhi
Name of publisher, distributor, etc. University of Delhi. Faculty of Inter- Disciplinary & Applied Science. Deptt. of Electronics Science
Date of publication, distribution, etc. 2022
300 ## - PHYSICAL DESCRIPTION
Extent 124p.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electronic Science
9 (RLIN) 867324
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Kabra Sneha Gu.
9 (RLIN) 867325
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Thesis
Holdings
Withdrawn status Lost status Damaged status Not for loan Home library Current library Date acquired Total Checkouts Barcode Date last seen Price effective from Koha item type
        Arts Library Arts Library 2026-01-14   TH0026718 2026-01-14 2026-01-14 Thesis